1. Field of the Invention
The present invention relates to a sample-and-hold circuit that stores the electric charge corresponding to an input voltage in a capacitor, and holds the potential thereof, and particularly to a sample-and-hold circuit that reduces the charge leakage due to the switches connected to the electrode of the capacitor, and suppresses the reduction in the held voltage.
2. Description of the Related Art
FIG. 4 is a circuit diagram for a capacitor array type D/A conversion circuit using a conventional sample-and-hold circuit.
This sample-and-hold circuit stores the charge corresponding to the voltage input from an input terminal VR in a capacitor C3, and holds the potential thereof. The held potential is amplified by an amplifier 10 connected to the capacitor C3, and the amplified voltage is output from an output terminal Vout to the outside.
The capacitor that stores the charge corresponding to the voltage input from the outside and holds the potential thereof is referred to as a xe2x80x9chold capacitorxe2x80x9d.
The operation of this conventional capacitor array type D/A conversion circuit will be described below. First, for initialization (reset), all of the one ends of the capacitors C0 to C2 are connected to the ground GND by switches SW0 to SW2, and a N-channel MOS transistor TN1 is turned on. Then, the amount of the charges which have been stored in the capacitors C0 to C3 becomes zero.
Next, in response to the digital signals input as signals to be D/A converted, one ends of the capacitors C0 to C2 are connected to a reference voltage terminal VR by the SW0 to SW2 switches, and then a N-channel MOS transistor TN1 is turned off. Here, for example, when one end of the capacitor C0 is connected to the ground GND by the switch SW0, the one ends of the capacitors C1 and C2 are connected to a reference voltage terminal VR by the switches SW1 and SW2, and the N-channel MOS transistor TN1 is turned off, a voltage output from the output terminal Vout is given by the following equation.
Vout=(Q3/C3)={(C1+C2)/C3}xc3x97VRxe2x80x83xe2x80x83(1)
where, C1 to C3 denotes the capacitances of the capacitors C1 to C3, respectively, and Q3 denotes the amount of the charge stored between both ends of the capacitor C3.
FIG. 5 is a circuit diagram for a switching comparator using a sample-and-hold circuit in accordance with another conventional example.
In FIG. 5, a sample-and-hold circuit is comprised of a capacitor C4, an inverter I1, and a N-channel MOS transistor TN3. By adding N-channel MOS transistors TN2 and TN4 to such a sample-and-hold circuit, a switching comparator is formed.
The operation of the switching comparator shown in FIG. 5 will be described using a timing chart shown in FIG. 6.
First, in a time period T1, the N-channel MOS transistors TN2 and TN3 are turned on, and the N-channel MOS transistor TN4 is turned off. The capacitor C4 is thereby initialized while an input voltage V1 is applied.
Then, in a time period T2, the N-channel MOS transistors TN2 and TN3 are turned off, and the N-channel MOS transistor TN4 is turned on. As a result, the output of the inverter I1 varies in response to the potential difference between the input voltage V1 and an input voltage V2. If V1 is larger than V2, an xe2x80x9cHxe2x80x9d level, that is, a power supply voltage VDD is output from the inverter I1. On the other hand, if V1 is smaller than V2, an xe2x80x9cLxe2x80x9d level, that is, a GND level is output from the inverter I1. In this way, the switching comparator compares magnitudes between input voltages V1 and V2, and outputs an xe2x80x9cHxe2x80x9d level or an xe2x80x9cLxe2x80x9d level.
Hereafter, after the time period T3, similar operations to the above-described time periods T1 and T2 are repeated.
FIG. 7 is a circuit diagram for a successive comparison type A/D conversion circuit using the above-described switching comparator.
In this A/D conversion circuit, each of N-channel MOS transistors TN11, TN12, TN13, etc. corresponds to the N-channel MOS transistor TN4 of the above-described switching comparator. The connection nodes in a ladder resistor comprising a plurality of resistors R are connected to the plurality of N-channel MOS transistors TN11, TN12, TN13 etc. Each of the plurality of N-channel MOS transistors selectively selects the voltage produced by the ladder resistor. Herein, a capacitor C4 stores the charge given by the following equation.
Q=C4xc3x97(Vinxe2x88x92Vb)xe2x80x83xe2x80x83(2)
where, Vb denotes the input voltage of the inverter I1 when the capacitor C4 has been initialized.
The operation of the A/D conversion circuit shown in FIG. 7 will be described using a timing chart shown in FIG. 8.
First, in a time period TO, the N-channel MOS transistors TN2 and TN3 are turned on, and all of the N-channel MOS transistors TN11, TN12, TN13, etc. are turned off. The capacitor C4 is thereby initialized while an analog signal Vin to be A/D converted is applied to.
Then, in a time period T1, the N-channel MOS transistors TN2 and TN3 are turned off, and the N-channel MOS transistor TN11 is turned on. As a result, the output of the inverter I1 varies in response to the potential difference between the input voltage Vin and a reference voltage VR1. If VR1 is smaller than Vin, an xe2x80x9cHxe2x80x9d level is output from the inverter I1. On the other hand, if VR1 is larger than Vin, an xe2x80x9cLxe2x80x9d level is output. In this manner, the switching comparator compares magnitudes between the input voltage Vin and the reference voltage VR1, and outputs an xe2x80x9cHxe2x80x9d level or an xe2x80x9cLxe2x80x9d level.
Next, in a time period T2, the N-channel MOS transistors TN2 and TN3 are turned off, and the N-channel MOS transistor TN12 is turned on. As a result, the output of the inverter I1 varies in response to the potential difference between the input voltage Vin and a reference voltage VR2. If VR2 is smaller than Vin, an xe2x80x9cHxe2x80x9d level is output from the inverter I1. On the other hand, if VR2 is larger than Vin, an xe2x80x9cLxe2x80x9d level is output. The switching comparator thus compares magnitudes between an input voltage Vin and the reference voltage VR2, and outputs an xe2x80x9cHxe2x80x9d level or an xe2x80x9cLxe2x80x9d level.
The same operation is performed for each time period after a time period T3. N-channel MOS transistors from a N-channel MOS transistor TN13 onward are successively turned on, reference voltages from a voltage VR3 onward are successively input, and reference voltages are successively compared with the input voltage Vin.
FIG. 9 is a circuit diagram for a sample-and-hold circuit in accordance with a third conventional example.
In this sample-and-hold circuit, the voltage input from an input terminal Vin is amplified by an amplifier 11, and the amplified voltage is output from an output terminal Vout. Also, the charge corresponding to the voltage input from the input terminal Vin is stored in a capacitor C5, and the potential is held by turning off a N-channel MOS transistor TN5. Even after the N-channel MOS transistor TN5 has been turned off, the held potential continues to be output.
In this manner, in each of these first to third conventional examples, the charge corresponding to the voltage input from the outside is stored in the capacitor, and thereby the potential thereof is held. However, even if the switches connected to the capacitor are turned off, the charge stored in the capacitor leaks as leakage currents via the switches.
Specifically, for example, in the first conventional example shown in FIG. 4, even if the N-channel MOS transistor that constitutes a switch is in the OFF state with its gate voltage being 0V, the charge stored in the capacitor C3 leaks as leakage currents via the N-channel MOS transistor TN1. Likewise, in the second conventional example shown in FIG. 5, the charge stored in the capacitor C4 leaks as leakage currents via the N-channel MOS transistor TN3 that is in the OFF state, and in the third conventional example shown in FIG. 9, the charge stored in the capacitor C5 leaks as leakage currents via the N-channel MOS transistor TN5 that is in the OFF state.
FIG. 10 is a diagram illustrating the leakage of the charge stored in the hold capacitor in the first conventional example.
In this diagram, the time period A is an initialization period that the charge is discharged and the next charge storage is prepared for. The time period B is a time period that the charge is stored and the potential is held, as well as the voltage output to the outside. Herein, the charge stored in the hold capacitor leaks as leakage currents via the switches connected thereto, and decreases with time. As shown in FIG. 10, for example, the amounts corresponding to charge amounts q1 or q2 become the loss portions due to the leakage currents flowing via the switches. Here, the difference in the amount of charge loss between q1 and q2 is attributable to the difference in the characteristics between transistors constituting the switches.
In this way, as the charge decreases, the held voltage also declines.
In the first conventional example, under ideal conditions that there is no leakage current, a voltage based on the above-described equation (1) is output. However, as shown in FIG. 10, when the charge Q3 stored in the capacitor C3 decreases, an intended voltage Vout cannot be achieved. The difference between the intended voltage and the voltage actually obtained corresponds to the above-described amounts of the charge losses q1 and q2.
Here, in order to speed up circuit operations, if the capacity of the hold capacitor is reduced and/or the on-resistances of the switches connected to the capacitor is decreased, such influences of leakage currents increase. Also, appropriate comparative operations in an A/D conversion and the like cannot be carried out when attempting to elongate a voltage output period.
To the contrary, in order to perform appropriate comparative operations, it is necessary to increase the capacity of the hold capacitor, and/or to increase the on-resistances of the switches. However, this, in turn, prevents an initialization operation from being appropriately achieved. That is, it takes longer time than necessary to discharge the charge stored in the hold capacitor, and/or to store enough charge in the hold capacitor up to the voltage input from the outside.
Thus, in the conventional sample-and-hold circuits, the avoidance of the influences of leakage currents, and the achievement of a desired accuracy are gained at the expense of operation speed.
The present invention has been made with a view to solving the above-described problems associated with the conventional art. The purpose of the present invention is to prevent the electric charge stored in a hold capacitor from leaking as leakage currents via the switches connected to the hold capacitor, to suppress the reduction of the voltage held in the hold capacitor, and to thereby improve the performance of the sample-and-hold circuit.
In order to achieve the above-described purpose, the present invention provides a sample-and-hold circuit that has a capacitor for storing the voltage input from the outside as an electric charge, and holding the potential thereof, and has the switches connected to the capacitor. The switches are constituted of a plurality of switches that are connected in series with each other. In this sample-and-hold circuit, the potential difference between both ends of the switch (referred to as a first switch or the input terminal side switch) connected to the side of the capacitor out of the plurality of switches, is set to zero or substantially zero, at least during the time period that the plurality of switches is in the OFF state.
Preferably, the plurality of switches are connected in series with each other, and is simultaneously turned on or off.
Also, preferably the first switch is connected to one electrode (referred to as a charge storage electrode) in which a charge is stored, out of both electrodes of the capacitor. Here, the other electrode (opposite electrode to the charge storage electrode) of the capacitor is provided with a predetermined potential.
Furthermore, it is preferable that the sample-and-hold circuit in accordance with the present invention further includes an equipotential setting circuit that sets the potential of one end of the first switch wherein the other end thereof is connected to the capacitor so that the potential difference between both ends of the switch becomes zero or substantially zero.
Also, preferably, each of the plurality of switches or the hold capacitor is formed of a MOS transistor.
Moreover, it is preferable that the equipotential setting circuit includes a differential amplifier having a first input terminal, a second input terminal, and an output terminal for outputting the voltage obtained by amplifying the potential difference between the first and second input terminals, and includes a switch (second switch) for connecting the interconnection node of the plurality of switches and the first input terminal. In this equipotential setting circuit, it is further preferable that one end of the capacitor is connected to the second input terminal, while the other end thereof is connected to the output terminal, and that the interconnection node of the plurality of switches and the first input terminal is connected by the second switch, during the time period that the plurality of switches is in the OFF state.
In addition, the equipotential setting circuit preferably has a buffer amplifier that amplifies the voltage at the interconnection node between one end of the capacitor and the input terminal of the amplifier, outputs the amplified voltage to the output terminal thereof, and has an amplification factor of xe2x80x9c1xe2x80x9d, and preferably has a switch that connects the interconnection node of these switches and the output terminal of the buffer amplifier, during the time period that these plurality of switches is in the OFF state.
The above and other objects, features, and advantages of the present invention will be clear from the following detailed description of the preferred embodiments of the invention in conjunction with the accompanying drawings.